Asymmetrically strained all-silicon multi-gate n-Tunnel FETs
نویسندگان
چکیده
0038-1101/$ see front matter 2010 Elsevier Ltd. A doi:10.1016/j.sse.2010.04.037 * Corresponding author. Tel.: +41 21 693 5633; fax E-mail address: [email protected] (M This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and Ion/Ioff characteristics. We demonstrate that a lateral strain profile corresponding to at least 0.2 eV band-gap shrinkage at the BTB source junction could act as an optimized performance Tunnel FET enabling the cancellation of the drain threshold voltage. To implement a real device, we demonstrate using GAA Si NW with asymmetric strain profile using two local stressor technologies to have >4–5 GPa peak of lateral uniaxial tensile stress in the Si NW. 2010 Elsevier Ltd. All rights reserved.
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